1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a word line decoder which transfers a high voltage in a flash memory device having a low operating voltage.
2. Description of the Related Art
As digital information communication networks such as the Internet through mobile terminals and cellular phones have grown, non-volatile semiconductor memory devices have been viewed as one of the main contenders for nonvolatile storage of information in mobile terminals. Non-volatile memories include flash memories which can electrically erase stored data in blocks of predetermined numbers of bits and electrically write data.
A flash memory device, which is comprised of a plurality of sectors each including a plurality of memory cells, erases memory cell data in units of a block (sector) and performs programming (writing) in units of a memory cell. Since NAND-type flash memory devices have a degree of integration and memory capacity similar to dynamic RAMs, the uses and applications of such NAND-type flash memories are being gradually increased.
A NAND-type flash memory device has a structure where a memory string in which a plurality of memory cells are connected in series to one another is connected between a bit line and a source line, wherein a plurality of memory strings constitutes a memory cell array.
FIG. 1 is a view illustrating a conventional flash memory device 100. Referring to FIG. 1, the flash memory device 100 includes a block memory cell array 110 and a word line decoder 120. The flash memory device 100 can include a plurality of block memory cell arrays, in which case word line decoders are positioned in such a manner that they correspond one-to-one to the block memory cell arrays. For the convenience of description, in this specification, only one word line decoder 120 and a corresponding block memory cell array 110 are described.
The block memory cell array 110 is comprised of memory strings CS which are respectively connected to n bit lines BL0, BL1, . . . , BLn−1. The memory strings CS are connected in common to a source line CSL. The gates of memory cells M0 through M15 in each memory string CS are respectively connected to word lines WL0 through WL15. The gates of string selection transistors SST for connecting the memory strings CS to the respective bit lines BL0, BL1, . . . , BLn−1 are connected to a string selection line SSL. The gates of ground selection transistors GST for connecting the memory strings CS to the common source line CSL are connected to a ground selection line GSL.
The word line decoder 120 selectively activates the string selection line SSL, the ground selection line GSL, and the word lines WL0 through WL15 of the memory cell array 110. The word line decoder 120 includes a decoding unit 122 which receives address signals ADDR and generates a block word line driving signal BLKWL, word line driving signals S0 through S15, a string selection voltage VSSL and a ground selection voltage VGSL and a word line driver 124 which transfers the word line driving signals S0 through S15, the string selection voltage VSSL and the ground selection voltage VGSL to the word lines WL0 through WL15, the string selection line SSL and the ground selection line GSL, respectively, in response to the block word line driving signal BLKWL.
The decoding unit 122 decodes the received address signals ADDR, and provides corresponding driving voltages (for example, a program voltage Vpgm, an erase voltage Verase, or a read voltage Vread) to each of the string selection line SSL, the word lines WL0 through WL15 and the ground selection line GSL, in a program operation, in an erase operation, or in a read operation. Also, the decoding unit 122 receives a high voltage Vpp and outputs it as the block word line driving signal BLKWL.
The word line driver 124 includes high-voltage pass transistors SN, WN0-WN15, GN, and CN, which are connected between the string selection voltage VSSL and the string selection line SSL, between the word line driving signals S0 through S15 and the word lines WL0 through WL15, between the ground selection voltage VGSL and the ground selection line GSL, and between the common source line voltage VCSL and the common source line CSL, respectively. The gates of the high-voltage pass transistors SN, WN0-WN15, GN, and CN are connected to each other and connected to the block world line driving signal BLKWL.
FIG. 2 is a circuit diagram of a circuit for generating the block word line driving signal BLKWL in the decoding unit 122.
Referring to FIG. 2, the decoding unit 122 makes the block word line driving signal BLKWL transition to a high voltage Vpp in response to a block selection signal BLKi. The block selection signal BLKi, which is generated by receiving and decoding address signals ADDR, is used when selecting a block memory cell array 110.
The block selection signal BLKi is input to a first inverter 201. An output of the first inverter 201 is input to a second inverter 202 and an output of the second inverter 202 is output as a word line driving signal BLKWL via an NMOS transistor 203 and a first depletion transistor 204. A supply voltage VDD is applied to the gates of the NMOS transistor 203 and the first depletion transistor 204. The first and second inverters 201 and 202 are driven by the supply voltage VDD.
The decoding unit 122 further includes a second depletion transistor 205 and a PMOS transistor 206 which are connected in series between a high voltage Vpp terminal and a block word line driving signal BLKWL line. The gate of the second depletion transistor 205 is connected to the block word line driving signal BLKWL line and the gate of the PMOS transistor 206 is connected to the output of the first inverter 201.
The decoding unit 122 forms an improper current path A resulting in an increase in power consumption if the supply voltage VDD falls below 1.8V, due to a low operating voltage of the flash memory device.
It is assumed that the threshold voltage Vth of the first and second depletion transistors 204 and 205 is about −2.2 V and the high voltage Vpp is about between 20 V and 22 V. If the block selection signal BLKi goes low, the output of the first inverter 201 goes high and the output of the second inverter 202 goes low. The output of the second inverter 202, which is low, is transmitted, via the NMOS transistor 203 and the first depletion transistor 204 and output as the block word line driving signal BLKWL.
Here, the PMOS transistor 206 must be turned off when the output of the first inverter 201 goes high. However, as the supply voltage VDD lowers, the PMOS transistor 206 is turned on.
If the block word line driving signal BLKWL goes to a ground voltage level grounded, the decoding unit 122 forms a DC current path A from the high voltage Vpp to the ground voltage GND via the second depletion transistor 205, the PMOS transistor 206, the first depletion transistor 204, the NMOS transistor 203 and an NMOS transistor (not shown) of the second inverter 202. Due to the DC current path A, power consumption increases.
Therefore, in order to reduce power consumption, a word line decoder which is capable of preventing an improper current path from being formed even when a supply voltage VDD falls, is needed.